Sciweavers

GLVLSI
2003
IEEE

Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers

14 years 4 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section of the accumulator that is not used to address the phase to amplitude mapping block thus reducing area, constraints in implementation, and up to 82% in power consumption compared to standard designs. Categories and Subject Descriptors B.6.1 [Logic Design]: Design Styles – Combinational Logic. B.7.1 [Integrated Circuits]: Types and Design Styles – VLSI. General Terms Performance, Design, Algorithms. Keywords Direct digital frequency synthesizer, DDFS, numerically controlled oscillator, NCO, low power, phase accumulator.
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where GLVLSI
Authors Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
Comments (0)