A Hardware-based Cache Pollution Filtering Mechanism for Aggressive Prefetches

Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between processors and memory subsystems. As smaller L1 caches prevail in deep submicron processor designs in order to maintain short cache access cycles, cache pollution caused by ineffective prefetches is becoming a major challenge. When too aggressive prefetching are applied, ineffective prefetches not only can offset the benefits of benign prefetches due to pollution but also throttle bus bandwidth, leading to overall performance degradation. In this paper, a hardware based cache pollution filtering mechanism is proposed to differentiate good and bad prefetches dynamically using a history table. Two schemes — Per-Address (PA) based and Program Counter (PC) based — for triggering prefetches are proposed and evaluated. Our cache pollution filters work in tandem with both hardware and software prefetchers. As s...

• Type: Conference
• Year: 2003
• Where: ICPP
• Authors: Xiaotong Zhuang, Hsien-Hsin S. Lee
• Keywords: Cache Pollution, Cache Pollution filters, Distributed And Parallel Computing, ICPP 2003, Ineffective Prefetches