Reactive Multi-Word Synchronization for Multiprocessors

Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hardware primitives such as compare-and-swap, load-linked/store-conditional and fetchand-op, from which the higher-level synchronization operations are then implemented in software. Although the single-word hardware primitives are conceptually powerful enough to support higher-level synchronization, from the programmer’s point of view they are not as useful as their generalizations to the multi-word objects. This paper presents two fast and reactive lock-free multi-word compare-and-swap algorithms. The algorithms dynamically measure the level of contention as well as the memory conflicts of the multi-word compare-and-swap operations, and in response, they react accordingly in order to guarantee good performance in a wide range of system conditions. The algorithms are non-blocking (lock-free), allowing in this ...

• Type: Conference
• Year: 2003
• Where: IEEEPACT
• Authors: Phuong Hoai Ha, Philippas Tsigas
• Keywords: Hardware, Hardware Primitives, IEEEPACT 2003, Multi-word Compare-and-swap Algorithms, Single-word Hardware Primitives