Some Modular Adders and Multipliers for Field Programmable Gate Arrays

This paper is devoted to the study of number representations and algorithms leading to efficient implementations of modular adders and multipliers on recent Field Programmable Arrays. Our hardware operators take advantage of the building blocks available in such devices: carrypropagate adders, memory blocks, and sometimes embedded multipliers. The first part of the paper describes three basic methodologies to carry out a modulo m addition and presents in more details the design of modulo (2n ± 1) adders. The major result is a novel modulo (2n +1) addition algorithm leading to an area-time efficient implementation of this arithmetic operation on FPGAs. The second part describes a modulo m multiplication algorithm involving small multipliers and memory blocks, and modulo (2n + 1) multipliers based on Ma’s algorithm. We also suggest some improvements of this operator in order to perform a multiplication in the group (Z∗ 2n+1, ·).

• Type: Conference
• Year: 2003
• Where: IPPS
• Authors: Jean-Luc Beuchat
• Keywords: Distributed And Parallel Computing, Efficient Implementation, IPPS 2003, Memory Blocks, Modular Adders