Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor

Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. The resulting speculative issuing of load instructions in these architectures can significantly impact the performance of the memory hierarchy as the system exploits higher degrees of parallelism. In this study, we investigate the effects of executing the mispredicted load instructions on the cache performance of a scalable multithreaded architecture. We show that the execution of loads from the wronglypredicted branch path within a thread, or from a wrongly-forked thread, can result in an indirect prefetching effect for later correctly-executed paths. By continuing to execute the mispredicted load instructions even after the instruction- or thread-level control speculation is known to be incorrect, the cache misses for the correctly predicted paths and threads can be reduced, typically from 42-73%. We introd...

• Type: Conference
• Year: 2003
• Where: IPPS
• Authors: Ying Chen, Resit Sendag, David J. Lilja
• Keywords: Concurrent Multithreaded Architecture, Distributed And Parallel Computing, IPPS 2003, Load Instructions, Multithreaded Architecture