High-speed VLSI architecture for parallel Reed-Solomon decoder

—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. Parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Hanho Lee
• Keywords: Euclidean Algorithm, Euclidean Algorithm Block, ISCAS 2003, Parallel Rs Decoders