Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs [8]. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 µm PD-SOI process.

• Type: Conference
• Year: 2003
• Where: ISVLSI
• Authors: Koushik K. Das, Richard B. Brown
• Keywords: Body Effects, ISVLSI 2003, Ultra-thin Gate Oxide, µm Pd-soi Process