Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA

In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures are scheduled rapidly with specific hardware resource/timing/architecture constraints from C/C++ level modeling by allocating the usage of functional units and real-time requirements. Using this methodology, a systemon-chip architecture for the next-generation CDMA system, i.e., HSDPA system, is prototyped rapidly. Advanced algorithms including chip-level equalizer, turbo codec and clock tracking, frequency offset compensation, are scheduled with Precesion C. A relatively more area/timing efficient RTL architecture is generated automatically and integrated with other design blocks in HDL designer, then implemented efficiently in Xilinx FPGAs. This new design flow demonstrates productivity improvement of 2X for typical wireless communication algorithms and reduces the risk of product development dramatically.

• Type: Conference
• Year: 2003
• Where: RSP
• Authors: Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro
• Keywords: Design Flow, Efficient Design Flow, HDL Designer, Rapid System Prototyping, RSP 2003