An integrated floorplanning with an efficient buffer planning algorithm

Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate the buffer planning with the floorplanning process. In this paper, we give an efficient buffer planning algorithm with linear complexity by computing all the feasible buffer insertion sites in a 2-step method. By partitioning all the dead spaces into blocks while doing the packing, the buffer allocation can be handled as an integral part in the floorplanning process. Our method is based on a simulated annealing approach which is divided into two phases: timing optimization phase and buffer insertion phase. Since there is more freedom for floorplan optimization, the floorplanning algorithm integrated with buffer planning can result in better time performance and chip area. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids – Placement and Routing General Terms Algorithms, Performance,...

• Type: Conference
• Year: 2003
• Where: ISPD
• Authors: Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
• Keywords: Buffer Insertion, Buffer Planning, Feasible Buffer Insertion, Hardware, ISPD 2003