On three-dimensional layout of pyramid networks

The pyramid networks are well-known as suitable structures for parallel computations such as image processing. This paper shows a practical 3D VLSI layout of the N-vertex pyramid network with volume O(N) and wire-length O( 3 √ N). Since the known best lower bounds for the volume and wire-length of a 3D layout for an N-vertex pyramid network are Ω(N) and Ω( 3 √ N/ log N), respectively, the volume of our layout is optimal, and the wire-length of our layout is close to the optimal.

• Type: Conference
• Year: 2002
• Where: APCCAS
• Authors: T. Yamada, N. Fujii, S. Ueno
• Keywords: APCCAS 2002, Hardware, N-vertex Pyramid Network, Practical 3d Vlsi, Pyramid Network