A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter

This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as the first stage and feature techniques such as common-mode stabilized active load, crosscoupled cascode connection, and close-loop pole placement. MOS switches are driven by bootstrapping circuits that do not subject the devices to large terminal voltages. The chip is being fabricated in a 0.5-µm CMOS technology. Simulation results have been checked for all process corners including the effect of 3σ capacitor mismatches, comparator offset, ±10% variation in polypoly capacitor and temperature variation from 0o C to 70o C. The results show that the converter has DNL less than 0.5LSB and achieves 59.3 dB SNDR at 100 kHz and 55.1dB at 15.1 MHz sinusoidal inputs. Power consumption is estimated at 34.8 mW.

• Type: Conference
• Year: 2002
• Where: APCCAS
• Authors: A. Tamtrakarn, N. Wongkomet
• Keywords: 10-bit Pipeline Adc, APCCAS 2002, Close-loop Pole Placement, Double Sampling Technique, Hardware