A Sum of Absolute Differences Implementation in FPGA Hardware

In this paper, we propose a new hardware unit that performs a 16 × 1 SAD operation. The hardware unit is intended to augment a general-purpose core. Further, we show that the 16 × 1 SAD implementation used can be easily extended to perform the 16 × 16 SAD operation, which is commonly used in many multimedia standards, including MPEG-1 and MPEG-2. We have chosen to implement the 16 × 1 SAD operation in field-programmable gate arrays (FPGAs), because it provides increased flexibility, sufficient performance, and faster design times. We performed simulations to validate the functionality of the 16×1 SAD implementation using the MAX+plus II (version 9.23 BASELINE) software from Altera and synthesis using the FPGA Express (version 3.4) software from Synopsis. Targeting the Altera’s FLEX20KE family, synthesis of our 16 × 1 SAD unit produced the following results for area and clock frequency: 1699 look-up tables (LUTs) and 197 MHz, respectively.

• Type: Conference
• Year: 2002
• Where: EUROMICRO
• Authors: Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
• Keywords: EUROMICRO 2002, Hardware, Hardware Unit, SAD Implementation, SAD Operation