A low power direct digital frequency synthesizer with 60 dBc spectral purity

We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ROM or multipliers are used, but an external DAC is required if an analog output is desired. Power consumption is 10 mW for a 100 MHz clock, which is significantly less than figures reported previously. System complexity is greatly reduced by using an efficient linear interpolation scheme to approximate a sinusoid function. This has resulted in silicon area utilization of 0.011 mm2 . The design would be suitable as an IP core in a low power digital RF transceiver ASIC. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – algorithms implemented in hardware, VLSI. General Terms Algorithms, Design, Performance. Keywords DDFS, DDS, phase to sine amplitude conversion, low power

• Type: Conference
• Year: 2002
• Where: GLVLSI
• Authors: J. M. Pierre Langlois, Dhamin Al-Khalili
• Keywords: DBc Spectral Purity, Digital Frequency Synthesizer, GLVLSI 2002, Low Power, VLSI