A compact delay model for series-connected MOSFETs

A compact delay model for series connected MOSFETs has been derived. This model enables accurate prediction of worst-case delay of different logic families such as dynamic logic. It also provides insight into delay change as the device parameters change. Key results show that the relative delay of series connected MOSFETs is almost invariant for different generations of technology.

• Type: Conference
• Year: 2002
• Where: GLVLSI
• Authors: Kaveh Shakeri, James D. Meindl
• Keywords: Compact Delay Model, GLVLSI 2002, Series Connected Mosfets, VLSI, Worst-case Delay