Multi-Output Timed Shannon Circuits

Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability are also included. Experimental results are given and analyzed for these techniques.

• Type: Conference
• Year: 2002
• Where: ISVLSI
• Authors: Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller
• Keywords: Circuit Switching, Circuit Switching Probabilities, ISVLSI 2002, Overall Circuit, VLSI