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EDCC
2010
Springer

How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

14 years 3 months ago
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining
Matthias Függer, Andreas Dielacher, Ulrich Sc
Added 19 Jul 2010
Updated 19 Jul 2010
Type Conference
Year 2010
Where EDCC
Authors Matthias Függer, Andreas Dielacher, Ulrich Schmid
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