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35

EDCC
2010
Springer

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256views Applied Computing» more EDCC 2010»

How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

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How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

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Matthias Függer, Andreas Dielacher, Ulrich Sc

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Applied Computing | EDCC 2010 |

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Added	19 Jul 2010
Updated	19 Jul 2010
Type	Conference
Year	2010
Where	EDCC
Authors	Matthias Függer, Andreas Dielacher, Ulrich Schmid

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