A memory coherence technique for online transient error recovery of FPGA configurations

The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of FPGAs can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications. Keywords Fault Tolerance, FPGA, ...

• Type: Conference
• Year: 2001
• Where: FPGA
• Authors: Wei-Je Huang, Edward J. McCluskey
• Keywords: FPGA, FPGA 2001, Memory Coherence, Memory Coherence Issue, User Applications