Implementation of (Normalised) RLS Lattice on Virtex

We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point prediction error. Internally, the computations are based on 32bit logarithmic arithmetic. On Virtex XCV2000E6, it takes 22% and 27% of slices respectively and performs at 45 MHz. The cores outperform (4-5 times) the standard DSP solution based on 32 bit floating point TMS320C3x/4x 50MHz processors.

• Type: Conference
• Year: 2001
• Where: FPL
• Authors: Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony Fagan
• Keywords: 24-bit Fixed Point, FPL 2001, Hardware, RLS Lattice, RLS Lattice Cores