An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars

This paper presents an FPGA-based implementation of a syntactic parser that can process languages generated by almost unrestricted real-life context-free grammars (CFGs). More precisely, we study the advantages o ered by a hardware implementation of a parallel version of an item-based tabular parsing algorithm adapted for word lattice parsing. A description of the parsing algorithm and of the associated hardware design is provided. A method called tiling, that allows a better processor and I/O bandwidth exploitation is introduced. Finally, an evaluation of the design performance on real-life data is given and the measured 244 speed-up factor makes our design a promising solution for Natural Language Processing applications, for which parsing speed is an important issue.

• Type: Conference
• Year: 2001
• Where: FPL
• Authors: Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cédric Chappelier
• Keywords: FPL 2001, Hardware, Parsing Algorithm, Tabular Parsing Algorithm, Word Lattice Parsing