Harmonious internal clock synchronization

Internal clock synchronization has been investigated, or employed, for quite a number of years, under the requirement of good upper bounds for the deviation, or accuracy, between a predefined master node M and slaves S1, S2, etc. It has been tacitly assumed that the accuracy range between slaves S1 and S2 was just the same as for the master/ slave. In extensive experimental studies of unicast-based protocols, however, we found a significantly worse accuracy between the slave nodes. Except for the asymmetry as such – which results in different communication conditions in a logically peer communication structure (like in our MELODY system) – this is particularly undesirable, if not harmful, if one wants to dynamically shift the master role between nodes, for the purpose of achieving fault tolerance. Nearly all previous internal clock synchronization algorithms with high accuracy are based on unicast messages (including our own efforts). In this paper we present two new broadcast pro...

• Type: Conference
• Year: 2000
• Where: ECRTS
• Authors: Horst F. Wedde, Wolfgang Freund
• Keywords: ECRTS 2000, Embedded Systems, Fault Tolerance, Internal Clock Synchronization, Master/ Slave