Configuration Relocation and Defragmentation for Reconfigurable Computing

Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute-intensive sections of a program to reconfigurable logic [Hauck98]. However, the number and frequency of these hardware-mapped sections of code are limited by the requirement that the speedups provided must outweigh the considerable cost of configuration. Research has shown that the ability to relocate and defragment configurations on an FPGA dramatically decreases the overall configuration overhead [Li00]. This increases the viability of mapping portions of the program that were previously considered to be too costly. We therefore explore the adaptation of the Xilinx 6200 series FPGA for relocation and defragmentation. Due to some of the complexities involved with this structure, we also present a novel architecture designed from the ground up to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA.

• Type: Conference
• Year: 2000
• Where: FCCM
• Authors: Katherine Compton, James Cooley, Stephen Knol, Scott Hauck
• Keywords: Compute-intensive Sections, FCCM 2000, Overall Configuration Overhead, Reconfigurable Logic, VLSI