Tunable Fault Tolerance for Runtime Reconfigurable Architectures

Fault tolerance is becoming an increasingly important issue, especially in mission-critical applications where data integrity is a paramount concern. Performance, however, remains a large driving force in the market place. Runtime reconfigurable hardware architectures have the power to balance fault tolerance with performance, allowing the amount of fault tolerance to be tuned at run-time. This paper describes a new builtin self-test designed to run on, and take advantage of, runtime reconfigurable architectures, using the PipeRench architecture as a model. In addition, this paper introduces a new metric by which a user can set the desired fault tolerance of a runtime reconfigurable device.

• Type: Conference
• Year: 2000
• Where: FCCM
• Authors: Steven K. Sinha, Peter Kamarchik, Seth Copen Goldstein
• Keywords: Fault Tolerance, FCCM 2000, Runtime Reconfigurable Architectures, Runtime Reconfigurable Hardware, VLSI