Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

39

GLVLSI
2000
IEEE

favoriteEmaildiscussreport

104views VLSI» more GLVLSI 2000»

A new technique for estimating lower bounds on latency for high level synthesis

14 years 3 months ago

A new technique for estimating lower bounds on latency for high level synthesis

Download www.cecs.uci.edu

In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application of interest. Our proposed technique can be used to compute a tighter earliest scheduling step for nodes (operations) in the Data Flow Graph and thus be used to improve the result quality of any technique requiring the computation of such Ë È values.

Helvio P. Peixoto, Margarida F. Jacome

Real-time Traffic

Data Flow Graph | Fast Estimation Technique | GLVLSI 2000 | Latency Lower Bounds | VLSI |

claim paper

Related Content

» Lower Bound Estimation for Low Power HighLevel Synthesis

» Effective Lower Bounding Techniques for PseudoBoolean Optimization

» Memory Estimation for High Level Synthesis

» CommonCase Computation A HighLevel Technique for Power and Performance Optimization

» Lower Upper Bound Estimation Method for Construction of Neural NetworkBased Prediction Int...

» High Level Synthesis of Degradable ASICs Using Virtual Binding

» Data communication estimation and reduction for reconfigurable systems

» Highlevel synthesis scheduling and allocation using genetic algorithms

» Concurrent flipflop and repeater insertion for high performance integrated circuits

Post Info
More Details (n/a)

Added	31 Jul 2010
Updated	31 Jul 2010
Type	Conference
Year	2000
Where	GLVLSI
Authors	Helvio P. Peixoto, Margarida F. Jacome

Comments (0)