Impact of Chip-Level Integration on Performance of OLTP Workloads

With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. Some current designs already integrate extremely large on-chip caches, and there are aggressive next-generation designs that attempt to also integrate the memory controller, coherence hardware, and network router all onto a single chip. The tight coupling of these modules will enable efficient memory systems with substantially better latency and bandwidth characteristics relative to current designs. Among the important application areas for high-performance servers, online transaction processing (OLTP) workloads are likely to benefit most from these trends due to their large instruction and data footprints and high communication miss rates. This paper examines the design trade-offs that arise as more system functionality is integrated onto the processor chip, and identifies a number of important architectura...

• Type: Conference
• Year: 2000
• Where: HPCA
• Authors: Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese
• Keywords: Chip-level Integration, Current Designs, Distributed And Parallel Computing, HPCA 2000, Large On-chip Caches