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IOLTS
2000
IEEE

Self-Testing of FPGA Delay Faults in the System Environment

14 years 3 months ago
Self-Testing of FPGA Delay Faults in the System Environment
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing.
Andrzej Krasniewski
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where IOLTS
Authors Andrzej Krasniewski
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