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IPPS
2000
IEEE

Design and Evaluation of I/O Strategies for Parallel Pipelined STAP Applications

14 years 5 months ago
Design and Evaluation of I/O Strategies for Parallel Pipelined STAP Applications
This paper presents experimental results for a parallel pipeline STAP system with I/O task implementation using the parallel file systems on the Intel Paragon and the IBM SP. In our previous work, a parallel pipeline model was designed for radar signal processing applications on parallel computers. Based on this model, we implemented a real STAP application which demonstrated the performance scalability of this model in terms of throughput and latency. In this paper, we study the effect on system performance when the I/O task is incorporated in the parallel pipeline model. There are two alternatives for I/O implementation: embedding I/O in the pipeline or having a separate I/O task. From these two I/O implementations, we discovered that the latency may be improved when the structure of the pipeline is reorganized by merging multiple tasks into a single task. All the performance results shown in this paper demonstrated the scalability of parallel I/O implementation on the parallel pip...
Wei-keng Liao, Alok N. Choudhary, Donald Weiner, P
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where IPPS
Authors Wei-keng Liao, Alok N. Choudhary, Donald Weiner, Pramod K. Varshney
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