Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow

The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the register array, there are no other dataflow macros used; it is fully designed with standard cell books and is placed flat with a timing driven placement algorithm. This design method allows more 'irregular' structures than usually found in custom designs. An overview of the floating-point unit is given and some interesting design items are shown: a 120 bit-wide truecomplement adder with precounting of leading zero digits, a signed multiplier with bit-optimized Wallace tree, intensive forwarding in source equal target cases and the checking method.

• Type: Conference
• Year: 1999
• Where: ARITH
• Authors: Guenter Gerwig, Michael Kroener
• Keywords: Applied Computing, ARITH 1999, Bit Fraction Dataflow, Bit-wide Multiplier, Floating-point Unit