Power estimation for architectural exploration of HW/SW communication on system-level buses

The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching activity of the on-chip and off-chip buses at the system-level has been defined to evaluate the power dissipation and to compare the effectiveness of power optimization techniques. The paper aims at providing a framework for architectural exploration of a system design, focusing on the power consumption estimation of memory communication. Experimental results, conducted on bus streams generated by a real microprocessor and a stream generator, show

• Type: Conference
• Year: 1999
• Where: CODES
• Authors: William Fornaciari, Donatella Sciuto, Cristina Silvano
• Keywords: CODES 1999, Overall Power Budget, Power Consumption, Power Consumption Estimation, Software Engineering