Yield Estimation of VLSI Circuits with Downscaled Layouts

This paper describes the yield estimation approach to layout scaling of submicron VLSI circuits. The presented method makes it feasible to find scaling factor of the IC design which is optimal from the manufacturing yield point of view. It also allows to reduce time-consuming extraction of the critical area functions. Examples of yield calculations using the proposed method are presented as well.

• Type: Conference
• Year: 1999
• Where: DFT
• Authors: Witold A. Pleskacz
• Keywords: DFT 1999, Submicron Vlsi Circuits, VLSI, Yield Estimation Approach, Yield Point