Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM

A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integrates four processing elements, a total of 16 Mbit DRAM, and application specific interfaces. A hierarchical test strategy has been developed to test the different structures of the system such as processing elements and embedded DRAM. Logic testing is controlled by a fault tolerant BIST controller. The DRAM macrocells are supplied with integrated test facilities and word line redundancy, resulting in a yield of 99.0% for a 4 Mbit DRAM macro. To avoid soft failures, an SEC-DED error correction code (ECC) scheme for the DRAM has been realized. Even though the implementation of the ECC results in an area overhead of about 12%, the overall system yield is not decreased due to the effects of the ECC on defect tolerance of the memory. The 4 cm2 multiprocessor system is suitable for utilization as a building block o...

• Type: Conference
• Year: 1999
• Where: DFT
• Authors: Markus Rudack, Dirk Niggemeyer
• Keywords: DFT 1999, DRAM, DRAM Process, Mbit DRAM, VLSI