The rapid progress in high-performance microprocessor design has made it di cult to adapt real-time scheduling results to new models of microprocessor hardware, thus leaving an unfortunate gap between real-time scheduling theory and its practice. In light of current and expected trends in commercial microprocessor architecture design, it is therefore important to make a qualitative assessment of how modern processor architectures contribute to this gap. This paper addresses the problem of how to schedule periodic, real-time threads on a class of architectures referred to as multi-level-context MLC architectures. Examples of such architectures are real-time operating systems with support for useror kernel-level threads, and multithreaded microprocessors endowed with on-chip contexts. A common feature of these architectures is that they provide support for the administration of threads within condi erent levels of abstraction. Therefore, the cost for switching between threads will depen...
Jan Jonsson, Henrik Lönn, Kang G. Shin