Scalable Hardware-Algorithms for Binary Prefix Sums

Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequence using, as basic building blocks, linear arrays of at most w 2 shift switches. An immediate consequence of this feature is that in our designs broadcasts are limited to buses of length at most w 2 making them eminently practical. Using our design, the sum of a w k-bit binary sequence can be obtained in the time of 2k 0 2 broadcasts, using 2w k02 + O(w k03 ) blocks, while the corresponding prefix sums can be computed in 3k 04 broadcasts using (k + 2)w k02 + O(kw k03 ) blocks.

• Type: Conference
• Year: 1999
• Where: IPPS
• Authors: Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya
• Keywords: Basic Building Blocks, Binary Sequence, Distributed And Parallel Computing, IPPS 1999, Prefix Sums