An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture

Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computations among image blocks are the most time consuming. In our method, processing elements (PEs) configured for each image block perform these computations in a pipeline manner. By configuring PEs, we can reduce the number of adders, which are the main computing elements, by half even in the worst case. This reduction increases the number of PEs that work in parallel. In addition, dynamic reconfigurability of hardware is employed to omit useless metric computations. Experimental results show that the resources for implementing the PEs are reduced to 60 to 70% and the omission of useless metric computations reduces the encoding time to 10 to 55%.

• Type: Conference
• Year: 1999
• Where: IPPS
• Authors: Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
• Keywords: Distributed And Parallel Computing, Image Block, IPPS 1999, Metric Computations, Useless Metric Computations