FPGA Implementation of Modular Exponentiation

An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs. One XC6000 chip, or 4 Kgates accommodates 132-bit long integers. 16 Kgates is required for modular exponentiation of 512 bit keys, with the estimated bit rate 800 Kb sec. 1 Systolic Array for Modular Exponentiation The design of public key cryptography hardware is an active area of research because the speed of cryptographical schemes is a serious bottleneck in many applications. A cheap and exible modular exponentiation hardware accelerator can be achieved using Field Programmable Gate Arrays. FPGA design presented in this paper is based on an e cient systolic array for a modular exponentiation such that the whole exponentiation procedure can be carried out entirely by the single systolic unit without use of global memory. This procedure is based on a Montgomery multiplication 2 , and uses a high-to-low bi...

• Type: Conference
• Year: 1999
• Where: IPPS
• Authors: Alexander Tiountchik, Elena Trichina
• Keywords: Distributed And Parallel Computing, IPPS 1999, Modular Exponentiation, Modular Exponentiation Hardware, Systolic Array