A Scalable Architecture for Montgomery Multiplication

Abstract. This paper describes the methodology and design of a scalable Montgomery multiplication module. There is no limitation on the maximum number of bits manipulated by the multiplier, and the selection of the word-size is made according to the available area and/or desired performance. We describe the general view of the new architecture, analyze hardware organization for its parallel computation, and discuss design tradeoffs which are useful to identify the best hardware configuration.

• Type: Conference
• Year: 1999
• Where: CHES
• Authors: Alexandre F. Tenca, Çetin Kaya Koç
• Keywords: Analyze Hardware Organization, CHES 1999, Cryptology, Discuss Design Tradeoffs, Scalable Montgomery Multiplication