Correlated Load-Address Predictors

As microprocessors become faster, the relative performance cost of memory accesses increases. Bigger and faster caches significantly reduce the absolute load-to-use time delay. However, increase in processor operational frequencies impairs the relative load-to-use latency, measured in processor cycles (e.g. from two cycles on the Pentium

• Type: Conference
• Year: 1999
• Where: ISCA
• Authors: Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri Weiser
• Keywords: Hardware, ISCA 1999, Load-address Prediction, Prediction, Prediction Rate