A Scalable Front-End Architecture for Fast Instruction Delivery

In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses, branch mispredictions, and taken branches in the instruction stream. To further complicate matters, a VLSI interconnect scaling trend is materializing that further limits the performance of front-end designs in future generation process technologies. To counter these challenges, we present a fetch architecture that permits a faster cycle time than previous designs and scales better with future process technologies. Our design, called the Fetch Target Buffer, is a multi-level fetch block-oriented predictor. We decouple the FTB from the instruction fetch and decode pipelines to afford it the fastest clock possib...

• Type: Conference
• Year: 1999
• Where: ISCA
• Authors: Glenn Reinman, Todd M. Austin, Brad Calder
• Keywords: Future Process Technologies, Hardware, Instruction Delivery Mechanism, ISCA 1999, Process Technologies