IP Validation for FPGAs Using Hardware Object Technology

Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional description of the circuit, with no timing consideration. On the other hand, simulation runs mainly on subsets of the entire input domain. Furthermore, these tools provide results in a format (e.g. state graphs, bit vectors or signal waves) that remain disconnected from the real output of the application. We introduce in this paper the process of validation applied to digital designs in FPGAs. It allows the designer the ability to test his/her implementation using the real data of the application and providing real results. With such real data, it becomes easier to identify where the error occurs and then to understand it.

• Type: Conference
• Year: 1999
• Where: FPL
• Authors: Steve Casselman, John Schewel, Christophe Beaumont
• Keywords: Entire Input Domain, FPL 1999, Hardware, Real Data, Simulation Tools