Improved Effective Capacitance Computations for Use in Logic and Layout Optimization

We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when the slew time is non-zero (i.e., a ramp). We then extend this effective capacitance algorithm to complex gates, i.e., channel-connected components. Preliminary experimental results using the new effective capacitance approach show that the resulting delay estimates are quite accurate

• Type: Conference
• Year: 1999
• Where: VLSID
• Authors: Andrew B. Kahng, Sudhakar Muddu
• Keywords: Cell Delay Calculation, Effective Capacitance, Effective Capacitance Approach, VLSI, VLSID 1999