Processor Modeling for Hardware Software Codesign

In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific embedded systems necessitate high level system design tools for rapid prototyping. This work involves design of a language Sim-nML which will be the base for a high level system design environment. The language is simple, elegant and powerful enough to express the behavior of the processor at instruction level. This language is used as the base for a whole set of tools such as assembler, disassembler and simulator generator. As a part of this work, we implemented an instruction set simulator generator which takes Sim-nML description of the processor as input and produces C++ code for performance simulator. We envisage the use of the generated simulator for cycle based analysis of the processor and for performance estimation of the system. This work is primarily an extension of nML[2] language.

• Type: Conference
• Year: 1999
• Where: VLSID
• Authors: V. Rajesh, Rajat Moona
• Keywords: Performance Estimation, Simulator Generator, Software Codesign Paradigm, VLSI, VLSID 1999