Reorganizing global schedules for register allocation

Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study how to perform global instruction scheduling before register allocation (prepass scheduling) for control-intensive non-numerical applications. As the number of parallel function units in modern microprocessors has increased, compiler writers have increased the size of prepass scheduling regions and the number of speculative operations scheduled. However, if prepass scheduling is not carefully managed, it is easy to create places in a prepass schedule that require more register resources than are architecturally available. We propose an approach that maintains the effectiveness of prepass scheduling in exploiting ILP even with the constraint of a limited number of architectural registers. In particular, we show that the pairing of a greedy prepass scheduler with a code reorganizer performs significantly better...

• Type: Conference
• Year: 1999
• Where: ICS
• Authors: Gang Chen, Michael D. Smith
• Keywords: Distributed And Parallel Computing, ICS 1999, Instruction Scheduling, Prepass Scheduling, Prepass Scheduling Regions