Verification of Timed Systems Using POSETs

This paper presents a new algorithm for efficiently verifying timed systems. The new algorithm represents timing information using geometric regions and explores the timed state space by considering partially ordered sets of events rather than linear sequences. This approach avoids the explosion of timed states typical of highly concurrent systems by dramatically reducing the ratio of timed states to untimed states in a system. A general class of timed systems which include both event and level causality can be specified and verified. This algorithm is applied to several recent timed benchmarks showing orders of magnitude improvement in runtime and memory usage.

• Type: Conference
• Year: 1998
• Where: CAV
• Authors: Wendy Belluomini, Chris J. Myers
• Keywords: CAV 1998, Hardware, Partially Ordered Sets, Timed State Space, Timed States