Buffer size optimization for full-search block matching algorithms

This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buger size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost.

• Type: Conference
• Year: 1997
• Where: ASAP
• Authors: Yuan-Hau Yeh, Chen-Yi Lee
• Keywords: ASAP 1997, Block Matching Algorithms, Hardware, I/O Bandwidth Constraint, Optimized Buffer Size