Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications

A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to the gate level. The methodology uses a C++-based untimed data ow system description, which is gradually re ned to an optimized, bit-true and clock cycle true C++-description. Through this renement, a bridge from link level design semantics to architectural VHDL semantics is made within one and the same environment.

• Type: Conference
• Year: 1997
• Where: DATE
• Authors: Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens
• Keywords: DATE 1997, Digital Modem, Digital Modem Design, Hardware, Link Level