A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement

Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing based placement has minimized area, but with deep submicron design, minimizing wirelength delay is also needed. The algorithm discussed in this paper is the first parallel algorithm for timing driven placement. We have used a very accurate Elmore delay model which is more compute intensive and hence the need for parallel placement is more apparent. Parallel placement is also needed for very large circuits that may not fit in the memory of a single processor. Therefore, our algorithm is circuit partitioned and can handle arbitrary large circuits on distributed memory multiprocessors. The algorithm, called mpiPLACE,has been tested on several large benchmarks on a variety of parallel architectures.

• Type: Conference
• Year: 1997
• Where: ICCD
• Authors: John A. Chandy, Prithviraj Banerjee
• Keywords: Hardware, ICCD 1997, Parallel Placement, Parallel Simulated Annealing, Simulated Annealing