System-Level Synthesis of Low-Power Hard Real-Time Systems

We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three degrees of freedom for power minimization, namely switching activity, effective capacity and voltage supply. We first define two key associated optimization problems, processor allocation and task assignment, and establish their computational complexity. Efficient algorithms are developed for both system design problems. The statistical analysis of comprehensive experimental results and their comparison with the developed conservative and optimistic sharp lower bounds, clearly indicates the quality of the proposed optimization techniques.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Darko Kirovski, Miodrag Potkonjak
• Keywords: Computer Architecture, DAC 1997, Hard Real-time Designs, Key Associated Optimization, User Specified Costs