A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders

A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level and register transfer level models. Executable specifications (pure functional software models, VHDL behavior models) are used to analyze the performance of different architectures. Hardware cost (area) and feasibility (timing) are determined by synthesis of RTL models. These models are generated directly out of the specification to avoid errors due to manual transformations and to reduce overall design time. Generator-based reuse modeling and hardware cost estimation is demonstrated using a decoder for MPEG variable length codes (VLC).

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Claus Schneider
• Keywords: Computer Architecture, DAC 1997, Functional Software Models, Hardware Cost, Transfer Level Models