Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT

We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based power estimation tool, Pythia, that blends the accuracy of low-level circuit simulators such as powermill with the speed of high level power estimators geared to design exploration. Pythia takes into account voltage-dependent capacitive nonlinearities and supports runtime adaptation of supply voltage. It employs a hybrid modeling aproach in which low-level simulation of logic gates and flip-flops can be combined with high level macromodels for memory structures where the energy per access is not as sensitive to input data statistics. The speed and accuracy of Pythia has enabled a detailed case study of two different approaches for the computation of the Inverse Discrete Cosine Transform, an integral component of the MPEG video coding algorithm. One approach uses conventional methods and the other exploits sig...

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha Chandrakasan
• Keywords: Computer Architecture, DAC 1997, Low-level Circuit Simulators, Pythia, Supply Voltage