A C-Based RTL Design Verification Methodology for Complex Microprocessor

Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the design cycle. In this paper, we suggest C language-based design and verification methodology to enhance the simulation speed instead of the conventional HDL-based methodologies. RTL C model(StreC7) describes the cycle-based behaviors of synchronous circuits and is followed by model refining and optimization using LifeTime Analyzer(LTA) and Cleanscr. The simulation speed of cycle-based C model makes it possible to test the RTL design with the L‘real-world”application programs in the order-of-magnitude faster speed than the commercial event-driven simulators. Using the proposed functional verification methodology, HK486, an intel 80486 - compatible microprocessor was successfully designed and verified. internal bus internal bus StreC clock cycle-based RTL register(FF,latch) Phil edge, Phil level Phi2 edge, Phi...

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung
• Keywords: Computer Architecture, DAC 1997, Functional Verification, Simulation Speed, Verification Methodology