Re-mapping for low power under tight timing constraints

In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algorithm based on Boolean relations that allows us to nd reduced-power replacements for clusters of more than one cell. Our approach is robust and scales well with circuit size: it has been tested on all largest examples of the MCNC91 benchmark suite. In average, power is reduced by more than 17 with no speed penalty compared to minimum delay implementations. Area is virtually unchanged.

• Type: Conference
• Year: 1997
• Where: ISLPED
• Authors: Patrick Vuillod, Luca Benini, Giovanni De Micheli
• Keywords: Hardware, ISLPED 1997, Mapped Netlist, Powerful Generalized Matching, Tight Timing Constraints